This content is from the following blog:
vlsiwizard.blogspot.com/2008/01/design-clock-divide-by-3-circuit-with.html
The basic insight was to notice that if you are doing a divide by 3 and want to keep the duty cycle at 50% you have to use the falling edge of the clock as well.
The trick is how to come up with a minimal design, implementing as little as possible flip-flops, logic and guaranteeing glitch free divided clock.
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I compiled some of the common FPGA interview questions I encountered over the years while seeking digital design positions:
1. FIFO depth calculation
How do you calculate the depth of the FIFO you need?
Fifo depth calculation:
Write clk freq – Fw
Read clk freq – Fr
Writing burst size: B
Idle clk cycle # for reading side – I
Fifo depth = B – B * Fr/(Fw*I)
Another approach (example with actual numbers): More
I think the short answer is yes. Cisco and others have developed strategies to deal with this threat, but fundamentally, the main idea under SDN and the promises it holds are incompatible with the existing platforms of these large network equipment providers, and their existing business models.
By decoupling the control plane and the data plane in the complex networking equipment, SDN (Software Defined Networking) makes it possible to simplify the design and development of computer networking hardware. It moves the complex control plane decisions to a remote server, and leaves only the physical layer and a limited layer 2 functionality in the networking hardware itself. It embodies all the recent trends in the computer industry such as the open source software development and cloud computing. Moving the control plane to a remote server is similar to the idea behind cloud computing, and the OpenFlow and OpenStack software that are widely used in the SDN networking equipment are open source software, which means anyone can use them to develop their own flavor of a network switch.
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The most important part of a digital system design is the interfaces. Each piece in the system, whether it is a device purchased from a vendor, or a re-used design clip that consists of multiple devices and their interconnects, or a programmable device such as an FPGA will probably be okay on their own. But what makes it a system is the interconnect of all these pieces. And that is where things go wrong.
There are various aspects of interface design. Let’s look at them one by one.
IO Technology
Designer needs to make sure that the IO driver and receiver technologies are compatible between two sides. For differential signalling, there are various IO technologies available, such as LVDS, LVPECL, CML, HSCL, etc to name a few. More