The most important part of a digital system design is the interfaces. Each piece in the system, whether it is a device purchased from a vendor, or a re-used design clip that consists of multiple devices and their interconnects, or a programmable device such as an FPGA will probably be okay on their own. But what makes it a system is the interconnect of all these pieces. And that is where things go wrong.
There are various aspects of interface design. Let’s look at them one by one.
Designer needs to make sure that the IO driver and receiver technologies are compatible between two sides. For differential signalling, there are various IO technologies available, such as LVDS, LVPECL, CML, HSCL, etc to name a few.
There are certain biasing and termination requirements for each of these IO types. They need to be followed closely. If the signal being transmitted in this interface is a DC balanced signal, AC coupling can be used on the differential line. In this case, since the dc bias point of each side of the AC coupling caps are separated, it becomes even more important to make sure both sides are biased properly. In the modern times, most vendors try to include the biasing and termination circuits inside the device both for receivers and transmitters. But sometimes external biasing will be needed. That is why the designer needs to pay close attention to the vendor documentation for the part, and understand any external biasing and termination requirements. Whether AC coupling or DC coupling is used, it is equially important to make sure the interface is biased and terminated properly.
Differential signals are typically used for high speed signalling. This suggests fast rise and fall times, and therefore it will be very likely that the propagation time of the signal will be comparable to the rise time of the signal, which means the line will be considered a transmission line. To minimize loss and reflections, it will be very important to terminate the line with an impedance equal to the characteristic impedance of the line. Again, nowadays it will be very likely that the receiver already includes internal termination (typically 100 ohm differential), but it is important to make sure that an external termination strategy is used if the line is not internally terminated.
There are documents and application notes on the vendor websites that can help with proper bias and termination strategies for differential IO technologies.
If the driver and receiver uses a different type of IO technology, this adds a different layer of complexity to the interface design. For example, if the driver is LVPECL, but the receiver is LVDS, then other than bias and termination, the designer also needs to make sure that the differential voltage swing level is compatible between the two sides. LVPECL typically have higher differential voltage levels than LVDS. So, people use resistor networks, or series resistors (to drop some voltage on them) to make sure the voltage levels seen by the receiver are not clipped. But this creates discontinuities in the transmission line and is not ideal for Signal Integrity purposes. But depending on the application and the interface speed, it can work fine, and is widely used, especially for things like clock signal connections. Many modern receivers are designed to accept up to 1V or 1.2V peak to peak differential swing levels nowadays, even if it is advertised as LVDS (which typically have lower swing, more like 600mV), so this becomes less of an issue lately. But one needs to pay attention to this, and ideally the same IO technology should be used on both sides.
There are ways to interface these different differental IO technologies with each other for DC coupled and AC coupled cases. Many application notes and other information can be found on the web about this. But the most important resource the designer should rely on is the device vendor’s documentation.
For single ended signals, IO technology is less of an issue, since it is almost always LVCMOS nowadays. But there are still things to pay attention to, such as whether we are connecting an open drain or a push pull driver to the receiver. If it is open drain, the output needs to be pulled up to the appropriate voltage rail.
For single ended clock signals, or other signals that transition frequently, it is also important to add a series source termination resistor, which may be needed.
The next important aspect of interface design is making sure the voltage levels match on both sides. This may sound obvious of course, and one might think there is no reason to even mention this requirement, but in today’s multi-voltage level world, it becomes easy to overlook voltage level mismatches between signals.
In the good old days, everything was 5V first, then later, everthing has become 3.3V. There was usually not much concern regarding the voltage level of interfacing signals. But as the speeds increased, and the geometries of the chip technologies got smaller, physics demanded that the voltage levels got lower as well. This created today’s digital world of silicon devices with multiple voltage levels. It is very common now to have complex ICs with 0.9V or 1.0V core voltage rails, with 1.5V, 1.8V or 2.5V IO or other rails. 3.3V rails are also still around, but it is becoming less and less common in the newest and the fastest chips. Many ICs now have multiple voltage rails, and interfacing signals from one IC to another one now also involves making sure the voltage level of the interfacing signals also match.
This makes voltage level translstor devices more and more common in complex digital systems.
Matching the voltage level of static or slowly changing signals can be easily achieved with typical voltage level translators, but fast changing signals, or signals that resemble clock signals create another challenge in this area. To be able to connect these signals between devices that have different voltage levels on each side, one needs to take the frequency of the signal into account, and make sure the voltage level translator can handle those frequencies. It may even be necessary to connect these signals with clock buffers that can support different voltage levels on each side, rather than typical voltage translators, since clock buffers are designed to work with clocks, and can typically support higher frequencies.
The direction of the signal is another factor to consider when interfacing signals at different voltage levels. If the signal is unidirectional, there isn’t much complication, and a unidirectional voltage translator can do the job. But interfacing bidirectional signals require using bidirectional voltage translators with or without direction pins. If we have a control signal that will indicate the direction of the transfer, a voltage translator with a direction pin will do the job. But there are also cases where we do not have a direction signal that indicates which side is the driver and which side is the receiver at any given time. I2C SDA signal is such an example. In those cases, a voltage translator with no direction pin is needed, and those devices also exist nowadays.
The number of receivers a driver will drive needs to be taken into account. The amount of current needed by each receiver, and the amount of current that can be provided by the driver will determine how many of these receivers the driver can drive directly. If more receivers need to be driven by the same signal, then extra buffer/driver devices are needed in between, to make sure the signals that go to each receiver have enough juice (can provide sufficient current).
Progation delay of the signal needs to be taken into account. If there are multiple signals that need to maintain a certain timing relationship with respect to one another, such as a clock signal, and a data signal that is aligned with this clock signal, higher propagation delay on one of these signals with respect to the other may break the timing relationship between them, and cause problems when the data is latched at the destination. In some cases, additional buffers/drivers, or even retimers between the source and destination may be needed, to regenerate the signals and their timing relationships.
For fast changing signals, if the propagation delay of the signal is comparable to the rise time of the signal, then the trace that carry this signal becomes a transmission line, and then proper termination techniques are also needed in those cases. Transmission line theory, termination, and impedance matching is a vast topic on its own, and we will not cover it in this article.
And the last important factor in the interface design that we want to cover in this article is the protocol of the interfacing signals. It is obvious that the correct messaging and handshaking is needed between both sides, and this requirement is probably the most obvious of them all. But still, it needs to be mentioned, and should be considered in interface design.