xilinx

I compiled some of the common FPGA interview questions I encountered over the years while seeking digital design positions:

1. FIFO depth calculation

How do you calculate the depth of the FIFO you need?

Fifo depth calculation:
Write clk freq – Fw
Read clk freq – Fr
Writing burst size: B
Idle clk cycle # for reading side – I

Fifo depth = B – B * Fr/(Fw*I)

Another approach (example with actual numbers): More